2.5g hz pll 锁定检测电路分析实现.doc

2.5G Hz PLL 锁定检测电路分析实现

目 录

摘要 I

ABSTRACT II

1引言 1

2 2.5G HZ PLL锁定检测电路工作原理分析 2

2.1 锁相环结构简介 2
2.2 锁相环的作用简介 2
2.3 锁定检测 3

3 2.5G HZ PLL锁定检测电路总体设计方案 5

3.1 概述 5
3.2 设计目标 6
3.3 顶层设计方案 7
3.4 验证与测试 11

4 2.5G HZ PLL锁定检测电路反向提取分析 12

4.1 锁定检测电路外部引脚 12
4.2 锁定检测电路内部结构 13
4.3 锁定检测电路的实现 15
4.4 反向提取的锁定检测电路图 16

5 2.5GHZ PLL锁定检测电路SMIC0.18工艺下重新设计 17

5.1 反相器设计 17
5.2 D触发器设计 18
5.3 计数器设计 18
5.4 十八输入或非门设计 19
5.5 与非门设计 20
5.6 时钟设计 21
5.7 锁定检测电路设计小结 21

6 2.5G HZ PLL 锁定检测电路HSPICE 下晶体管级仿真 22

6.1 触发器模块仿真测试 22
6.2 异或门仿真测试 23
6.3 十八输入或非门仿真测试 24
6.4 与非门仿真测试 25
6.5 锁定检测电路整体仿真测试 26

7 2.5G HZ PLL 锁定检测电路VERILOGHDL 语言描述 30

7.1 基本模块的描述 30
7.2 锁定检测电路的整体描述 32

8 结论 33

致 谢 84

参考文献 84

 
摘  要

在集成电路设计中，需要使芯片上内部时钟和外部时钟同步，希望在外部时钟输入的高频率下使用芯片的内部时钟。基于以上两点，锁相环常常用于产生芯片上的内时钟。但是随着处理器频率的提高，传统的数字锁相环已经不能满足要求。在本文中，我们将展现一个新的锁相环锁定检测方法。锁定检测的功能是检测锁相环是否达到锁定。2.5G Hz PLL 锁定检测电路分析实现，就是要完成锁定检测电路的正向总体设计方案，锁定检测电路的反向提取，再在反向提取电路的基础上在SMIC0.18 um 工艺下进行重新设计，并完成HSPICE下的晶体管级仿真。2.5G Hz PLL 锁定检测电路分析实现的难点与重点是反向电路的提取和SMIC0.18 工艺下的重新设计。
本文所讨论的锁相环能够锁定更高频率的时钟。该锁定检测电路采用比较成熟的SMIC0.18 um工艺。锁相环的压控震荡器的输出频率可以高达2.5GHZ。另外，该锁相环能够锁定高达到2.5GHZ 的输出频率。我们采用模拟电路来代替以往的数字的锁定检测电路。在SMIC0.18 um工艺下，采用本文所讨论的锁定检测电路而设计的锁相环相对其他的锁相环而言，具有更大的优越性。

关键词：锁相环  锁定检测  SMIC0.18um工艺  集成电路

Abstract

In integrated circuit design,we need to make the internal clock and the exterior clock of the chip synchronous, we also hope to use the internal clock of the chip under the high frequency clock of the exterior .According to the above , Phase-locked loops (PLLs) are usually used to create inside clock of the chip .But along with the exaltation of the processor frequency, the traditional digital PLL has already can't satisfy the request. In this paper, a new method of PLL lock detector will be presented. The function of the PLL lock detector is to test PLL whether attain to target or not. The analysis and realization of the 2.5 GHz PLL lock detector is to complete total design project,  to complete the anti- to distill of circuit, base on the anti- to distill of the circuit and carry on re- designing in the process of SMIC0.18um, and complete the HSPICE simulation of the transistor class .The difficulty and importance of analysis and realization of circuit of 2.5 GHz PLL lock detector is the anti- to distill of the circuit and re-design under the process of SMIC0.18um.
The PLL this text discussed can target the clock which has a higher frequency. the lock detector circuit adoption the process of SMIC0.18um which is more mature now. The output of the VCO can be up to the 2.5 GHz. Moreover, the lock detector circuit is able to lock to form a 2.5 GHz output signal .We adoption the analog circuit instead of digital lock detector circuit. A PLL based on this type of lock detector demonstrated superior performance over other PLLs in this SMIC0.18um process.

Key Words: PLL,lock detector,SMIC0.18um, integrated circuit