基于vhdl数字频率计的设计与仿真.doc

基于VHDL数字频率计的设计与仿真

目录
1 绪论 1
1.1 课题简介 1
1.2 课题研究背景 2
1.3 课题设计意义和目的 3
2 数字频率计的综合设计 5
2.1 设计原理 5
2.2 设计功能 5
2.3 设计思路 6
3 利用VHDL语言设计频率计 8
3.1 VHDL语言介绍 8
3.2 频率计的设计程序 9
4 数字频率计的仿真及波形分析 15
4.1 MAX+PLUS II软件简介 15
4.2 MAX+plus II的文本输入设计方法 16
4.3 系统设计仿真及波形分析 25
5 小结 32
致谢 33
附录：频率计源程序及模块图 34
参考文献 41

摘要：数字频率计是数字电路中的一个典型应用，实际的硬件设计用到的器件较多，连线比较复杂，而且会产生比较大的延时，造成测量误差、可靠性差。本课题介绍一种运用MAX+PLUSⅡ软件基于VHDL的采用自顶而下 (up to bottom ) 设计方法实现的数字频率计。根据频率计的基本原理, 运用自顶向下的设计思想,编程时分别对控制、计数、锁存、译码等电路模块进行VHDL文本描述 ,使每个电路模块以及器件都以文本的形式出现 ,然后通过编译、波形分析、仿真、调试来完善每个器件的功能。单个器件制作完成后 ,将它们生成库文件 ,并产生相应的符号,最后用语言将各个已生成库文件的器件的各个端口连接在一起 ,从而形成了系统主电路的软件结构。该设计方法与传统的设计方法相比,具有外围电路简单,程序修改灵活和调试容易等特点,实现数字系统硬件的软件化。
关键字：VHDL;频率计; MAX+PLUSⅡ
中图分类号：TP312

 
Digital frequency meter based on VHDL Design and Simulation

Abstract: Digital frequency meter is a digital circuit in a typical application, the actual hardware design of devices used in more complicated connection, but will have larger delay, caused by measurement error, poor reliability. This issue introduces a use of MAX + PLUS Ⅱ software is based on the use of VHDL top-down (up to bottom) design method to achieve the digital frequency meter. According to the basic principle of frequency meter, using top-down design, and programming the control, respectively, counting, latch, decoder circuit modules such as VHDL text description, so that each circuit module and the device is in text form , and then compile, waveform analysis, simulation, debugging to improve the function of each device. Produced a single device, will they generate library files, and generates a corresponding symbol, the final language will have generated libraries of various devices connected to each port, the main circuit to form the system software structure. The design method and the traditional design method, a simple peripheral circuits, application to modify the characteristics of a flexible and easy to debug, hardware-software implementation of digital systems.
Keywords: VHDL; frequency meter; MAX+PLUSⅡ