毕业设计 锁相环频率合成器.doc
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毕业设计 锁相环频率合成器,锁相环频率合成器全文52页 约21000字论述详细td-scdma(时分双工同步码分多址)是我国提出的具有自主知识产权的第三代移动通信空中接口标准，具有频谱利用率高、支持多种通信接口、与传统系统兼容性好、系统设备成本低和系统稳定性好等特点。其中射频收发信机是系统中的关键部件，从一定意义上决定了整个系统的通信质量。随着集...
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锁相环频率合成器
全文52页 约21000字 论述详细
TD-SCDMA(时分双工同步码分多址)是我国提出的具有自主知识产权的第三代移动通信空中接口标准，具有频谱利用率高、支持多种通信接口、与传统系统兼容性好、系统设备成本低和系统稳定性好等特点。其中射频收发信机是系统中的关键部件，从一定意义上决定了整个系统的通信质量。随着集成电路制造工艺和无线通信技术的迅速发展,实现全集成、多制式、低成本的无线收发器已成必然趋势。频率合成器作为无线收发器中的核心单元电路,是决定收发器性能好坏的关键因素,也是实现全集成无线收发器的主要难点。
本文系统地阐述了锁相环频率合成器的基本工作原理，较深入地分析了锁相环路的组成和工作过程，建立其相位模型以及动态方程，并且对环路的线性特性和噪声特性进行了详细的分析。在此基础上，针对TD-SCDMA系统的技术特点，以集成数字锁相芯片为核心精心设计了频率合成电路，构成了多频点输出频率合成器。本文对锁相环路各个重要组成部分的参数进行详细的分析计算，仔细设计了原理图。为了改善环路的捕获性能，进一步抑制鉴相器输出电压中的载频分量和高频噪声，降低由VCO控制电压的不纯而引起的寄生输出以及其他各种杂散噪声，对环路滤波器进行了重点设计，对多种方案进行分析和比较，合理选择和计算了环路的参数，进而使得集成锁相环频率合成电路的功能得到了充分发挥，为TD-SCDMA系统提供了良好的本振源。最后我们给出了测试的方法以及测试结果。
关键词：TD-SCDMA；锁相环；频率合成；VCO；环路滤波
ABSTRACT
TD-SCDMA (Time Division Synchronous CDMA)is one of the main flow Air Interface Criterions of 3G Communication Technology which is presented by China. TD-SCDMA has the noticeable advantages such as high一usage frequency spectrum, support various air interfaces, excellent compatibility with 2Gsystem, outstanding stability and the lower cost. Transceiver is the core component of the TD-SCDMA, to some extent, it plays the important role of the quality of the system. With the rapid development of IC (integrated circuits) fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation.
This paper expatiates on foundational principles of the PLL-Frequency Synthesizer, analyzes the performance procedure and constitution of the PLL. In this paper, the author both builds the phase model and dynamic equation and studies the linear and noise characteristic of the PLL in detail. Via to the previous analysis, the model parameter and the property of TD-SCDMA system.
the author decides to adopt the transceiver scheme: Digital IF and one order conversion in analog. Moreover, the multiple frequency points output frequency synthesizer lies on the digital PLL IC. In the article, the author designs the schematic diagram. In order to improve loop acquisition, furthermore, reject higher-order harmonic and noise in the output voltage of the PD, reduce any other stray noises and parasitic component output which is due to impurity of control voltage by VCO. During the course of design process, on one hand, comparing and analyzing among the various design schemes, on the other hand, elaborately computing and selecting the parameters of the phase locked loop. Further more, it is obvious that the performance of the frequency synthesizer is enhanced distinctly. In addition, there is no denying that the outstanding local oscillator makes the system performance improved sharply. Finally, the simulation results and measurements of the whole circuit are displayed in the end of the article.
Key words: TD-SCDMA； PLL； VCO； Frequency Synthesizer,；Loop Filter
目 录
1 绪论 ……………………………………………………………………………19
1.1、3G技术简介 ……………………………………………………………19
1.2 TD-SCDMA简介 …………………………………………………………20
1.3 本文的研究意义…………………………………………………………23
2 锁相环的系统原理分析 ………………………………………………………24
2.1 锁相环的基本组成………………………………………………………24
2.2 锁相环的工作原理………………………………………………………25
2.3 泵锁相环的基本组成 ……………………………………………………27
2.4 泵锁相环的基本工作原理 ………………………………………………28
2.5 三阶电荷泵锁相环的稳定性分析 ………………………………………28
3 频率合成器设计 ………………………………………………………………31
3.1 总体设计 …………………………………………………………………31
3.2 锁相环频率合成器芯片原理图设计 ……………………………………33
3.3 芯片各部分功能介绍 ……………………………………………………35
4 系统的调试与测试 ……………………………………………………………44
4.1 调试注意的要点 …………………………………………………………44
4.2 本振的测试及结果 ………………………………………………………45
5 总结 ……………………………………………………………………………49
参考文献……………………………………………………………………………
致谢…………………………………………………………………………………
附录…………………………………………………………………………………
部分参考文献
[23]张剑宇，孙承缓，来金梅，章倩荃.2. 4GHz频率合成器可编程分频器设计与实现
[24]复旦学报(自然科学版):2005(Vol. 44 No. 1) :140^143
[25]J. Parker, D. Ray. A low-noise 1. 6GHz CMOS PLL with on-chip loop filter.Proc. of the IEEE 1997 Cus七om Integrated Circuits Conference, SantaClara, USA. 1997:407^410
[26]S. M.Shahruz. Design of high-performance phase-locked loops and syn-thesizers. Journal of sound and vibra七ion. 2001(vol. 244 No. 2):367^377
全文52页 约21000字 论述详细
TD-SCDMA(时分双工同步码分多址)是我国提出的具有自主知识产权的第三代移动通信空中接口标准，具有频谱利用率高、支持多种通信接口、与传统系统兼容性好、系统设备成本低和系统稳定性好等特点。其中射频收发信机是系统中的关键部件，从一定意义上决定了整个系统的通信质量。随着集成电路制造工艺和无线通信技术的迅速发展,实现全集成、多制式、低成本的无线收发器已成必然趋势。频率合成器作为无线收发器中的核心单元电路,是决定收发器性能好坏的关键因素,也是实现全集成无线收发器的主要难点。
本文系统地阐述了锁相环频率合成器的基本工作原理，较深入地分析了锁相环路的组成和工作过程，建立其相位模型以及动态方程，并且对环路的线性特性和噪声特性进行了详细的分析。在此基础上，针对TD-SCDMA系统的技术特点，以集成数字锁相芯片为核心精心设计了频率合成电路，构成了多频点输出频率合成器。本文对锁相环路各个重要组成部分的参数进行详细的分析计算，仔细设计了原理图。为了改善环路的捕获性能，进一步抑制鉴相器输出电压中的载频分量和高频噪声，降低由VCO控制电压的不纯而引起的寄生输出以及其他各种杂散噪声，对环路滤波器进行了重点设计，对多种方案进行分析和比较，合理选择和计算了环路的参数，进而使得集成锁相环频率合成电路的功能得到了充分发挥，为TD-SCDMA系统提供了良好的本振源。最后我们给出了测试的方法以及测试结果。
关键词：TD-SCDMA；锁相环；频率合成；VCO；环路滤波
ABSTRACT
TD-SCDMA (Time Division Synchronous CDMA)is one of the main flow Air Interface Criterions of 3G Communication Technology which is presented by China. TD-SCDMA has the noticeable advantages such as high一usage frequency spectrum, support various air interfaces, excellent compatibility with 2Gsystem, outstanding stability and the lower cost. Transceiver is the core component of the TD-SCDMA, to some extent, it plays the important role of the quality of the system. With the rapid development of IC (integrated circuits) fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation.
This paper expatiates on foundational principles of the PLL-Frequency Synthesizer, analyzes the performance procedure and constitution of the PLL. In this paper, the author both builds the phase model and dynamic equation and studies the linear and noise characteristic of the PLL in detail. Via to the previous analysis, the model parameter and the property of TD-SCDMA system.
the author decides to adopt the transceiver scheme: Digital IF and one order conversion in analog. Moreover, the multiple frequency points output frequency synthesizer lies on the digital PLL IC. In the article, the author designs the schematic diagram. In order to improve loop acquisition, furthermore, reject higher-order harmonic and noise in the output voltage of the PD, reduce any other stray noises and parasitic component output which is due to impurity of control voltage by VCO. During the course of design process, on one hand, comparing and analyzing among the various design schemes, on the other hand, elaborately computing and selecting the parameters of the phase locked loop. Further more, it is obvious that the performance of the frequency synthesizer is enhanced distinctly. In addition, there is no denying that the outstanding local oscillator makes the system performance improved sharply. Finally, the simulation results and measurements of the whole circuit are displayed in the end of the article.
Key words: TD-SCDMA； PLL； VCO； Frequency Synthesizer,；Loop Filter
目 录
1 绪论 ……………………………………………………………………………19
1.1、3G技术简介 ……………………………………………………………19
1.2 TD-SCDMA简介 …………………………………………………………20
1.3 本文的研究意义…………………………………………………………23
2 锁相环的系统原理分析 ………………………………………………………24
2.1 锁相环的基本组成………………………………………………………24
2.2 锁相环的工作原理………………………………………………………25
2.3 泵锁相环的基本组成 ……………………………………………………27
2.4 泵锁相环的基本工作原理 ………………………………………………28
2.5 三阶电荷泵锁相环的稳定性分析 ………………………………………28
3 频率合成器设计 ………………………………………………………………31
3.1 总体设计 …………………………………………………………………31
3.2 锁相环频率合成器芯片原理图设计 ……………………………………33
3.3 芯片各部分功能介绍 ……………………………………………………35
4 系统的调试与测试 ……………………………………………………………44
4.1 调试注意的要点 …………………………………………………………44
4.2 本振的测试及结果 ………………………………………………………45
5 总结 ……………………………………………………………………………49
参考文献……………………………………………………………………………
致谢…………………………………………………………………………………
附录…………………………………………………………………………………
部分参考文献
[23]张剑宇，孙承缓，来金梅，章倩荃.2. 4GHz频率合成器可编程分频器设计与实现
[24]复旦学报(自然科学版):2005(Vol. 44 No. 1) :140^143
[25]J. Parker, D. Ray. A low-noise 1. 6GHz CMOS PLL with on-chip loop filter.Proc. of the IEEE 1997 Cus七om Integrated Circuits Conference, SantaClara, USA. 1997:407^410
[26]S. M.Shahruz. Design of high-performance phase-locked loops and syn-thesizers. Journal of sound and vibra七ion. 2001(vol. 244 No. 2):367^377
