组合电路测试生成算法研究——毕业论文.doc
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组合电路测试生成算法研究——毕业论文,摘要集成电路又称为ic(integrated circuits)，是在硅板上集合多种电子元器件实现某种特定功能的电路模块。它是电子设备中最重要的部分，承担着运算和存储的功能。集成电路的应用范围覆盖了军工、民用的几乎所有的电子设备。可以说集成电路是计算机业、数字家电业、通信等行业的绝对“心脏”。随着微电子技术的发展，集成...
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摘 要
集成电路又称为IC(Integrated Circuits)，是在硅板上集合多种电子元器件实现某种特定功能的电路模块。它是电子设备中最重要的部分，承担着运算和存储的功能。集成电路的应用范围覆盖了军工、民用的几乎所有的电子设备。可以说集成电路是计算机业、数字家电业、通信等行业的绝对“心脏”。
随着微电子技术的发展，集成电路的规模越来越大，结构越来越复杂，集成电路的测试生成变得越来越难，花费的时间也越来越多。对于大规模的集成电路，传统的测试生成算法已不再适用，寻找新型、有效的测试生成算法已成为一个重要的研究课题。
组合电路单固定型故障模型是国际上研究最早，也是采用最普遍的故障模型。实践表明，只要单固定型故障的覆盖率达到90%以上，那么单固定型故障的测试集也能检测其它类型的故障，例如多故障和桥接故障。又因为系统在调试阶段发生多故障的概率较大，但在使用阶段发生单固定型故障的可能性要大得多，因此，单固定型故障的测试生成问题一直是国际上研究的热点。从理论上讲，单固定型故障的测试生成问题早在六十年代就己经解决了。然而，理论分析证明，自动测试生成的时间复杂性是个NP完全问题。随着电路规模的增大，测试生成越来越困难。因此，加速测试生成，提高测试生成效率一直为人们所关注。
本文采用单固定型故障模型，对组合电路的测试生成进行了研究。以提高故障覆盖率和减小测试生成时间为主要目标，重点研究了以下内容：
1．综述了测试生成技术的研究现状和发展概况。
2．研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
3．研究了组合电路基于搜索状态控制的测试生成算法。
4．研究了组合电路多故障的测试生成算法。
关键词 测试生成；固定型故障；时滞故障
Research of the Test Generation Algorithm for the Combinational Circuit
Abstract
Integrated circuit can be called IC for short, and it is a modular circuit that assembles multiple electronic components on the silicon board to fulfill some specific function. IC is the most important part in the electronic device, and it undertakes the functions of operating and storing. IC can be applied to almost all the electronic devices for civil use and military project. IC can be called the absolute “heart” for the computer, the digital domestic electricity, the communication and so on.
With the development of the microelectronic technique, the scale of the integrated circuits become more and more large, the structure become more and more complex, and the test generation for the integrated circuits is becoming increasingly difficult and time consuming. The traditional test generation algorithms are extremely inefficient for the large-scale circuits. Consequently, new and cost-effective algorithms are imperative research subjects today.
The single stuck-at fault model for combinational circuit is a fault model researched at the earliest internationally, and it is also the one used mostly. Practice shows that the test set for single stuck-at fault can test other kind fault, e.g. multi-fault and bridging fault, if only fault coverage for single stuck-at fault attains above 90%. Because the probability of happening multi-fault for system is big during debug phase and the possibility of happening single fault is bigger during usage phase, the test generation problem for single stuck-at fault is the hot spot of research internationally. On paper, it has solved earlier than 60 times. But theoretical analyze proofs that time complexity for automatic test generation is a NP-completeness problem. As the augment of circuit scale, test generation becomes more and more difficult. Therefore, accelerating test generation and improving its efficiency is noticed all along.
This paper uses the single stuck-at fault model and selects the combinational circuits as research targets. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following:
1. The development and current research status of the test generation is introduced in this paper.
2. The test generation algorithm for non-robust path delay fault in combination- al circuits is studied.
3. Test generation algorithm based on search state dominance for combinational circuits is studied.
4. A test generation algorithm in combinational circuits is studied.
Keywords test generation, stuck-at fault, delay fault
目录
摘 要 I
Abstract III
第1章 绪论 1
1.1 测试生成算法的相关概念 2
1.1.1 测试生成的基本概念 .2
1.1.2 故障模型及模型化故障 3
1.2 测试生成算法概述 6
1.2.1 测试生成算法的研究现状 6
1.2.2 测试生成的发展趋势 8
1.3 课题的背景及研究内容 9
1.3.1 课题的背景 9
1.3.2 课题的主要研究内容 10
第2章 基于时滞故障的组合电路测试生成算法 11
2.1 时滞故障测试的基本知识 11
2.1.1 时滞故障模型 11
2.1.2 时滞测试的硬件模型 12
2.1.3 鲁棒性测试与非鲁棒性测试 13
2.2 基于固定型故障测试生成的时滞故障测试生成 14
2.2.1 基本知识 15
2.2.2 算法描述 17
2.2.3 实验结果 19
2.3本章小结 19
第3章 基于状态控制的组合电路测试生成算法 20
3.1 ..
集成电路又称为IC(Integrated Circuits)，是在硅板上集合多种电子元器件实现某种特定功能的电路模块。它是电子设备中最重要的部分，承担着运算和存储的功能。集成电路的应用范围覆盖了军工、民用的几乎所有的电子设备。可以说集成电路是计算机业、数字家电业、通信等行业的绝对“心脏”。
随着微电子技术的发展，集成电路的规模越来越大，结构越来越复杂，集成电路的测试生成变得越来越难，花费的时间也越来越多。对于大规模的集成电路，传统的测试生成算法已不再适用，寻找新型、有效的测试生成算法已成为一个重要的研究课题。
组合电路单固定型故障模型是国际上研究最早，也是采用最普遍的故障模型。实践表明，只要单固定型故障的覆盖率达到90%以上，那么单固定型故障的测试集也能检测其它类型的故障，例如多故障和桥接故障。又因为系统在调试阶段发生多故障的概率较大，但在使用阶段发生单固定型故障的可能性要大得多，因此，单固定型故障的测试生成问题一直是国际上研究的热点。从理论上讲，单固定型故障的测试生成问题早在六十年代就己经解决了。然而，理论分析证明，自动测试生成的时间复杂性是个NP完全问题。随着电路规模的增大，测试生成越来越困难。因此，加速测试生成，提高测试生成效率一直为人们所关注。
本文采用单固定型故障模型，对组合电路的测试生成进行了研究。以提高故障覆盖率和减小测试生成时间为主要目标，重点研究了以下内容：
1．综述了测试生成技术的研究现状和发展概况。
2．研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
3．研究了组合电路基于搜索状态控制的测试生成算法。
4．研究了组合电路多故障的测试生成算法。
关键词 测试生成；固定型故障；时滞故障
Research of the Test Generation Algorithm for the Combinational Circuit
Abstract
Integrated circuit can be called IC for short, and it is a modular circuit that assembles multiple electronic components on the silicon board to fulfill some specific function. IC is the most important part in the electronic device, and it undertakes the functions of operating and storing. IC can be applied to almost all the electronic devices for civil use and military project. IC can be called the absolute “heart” for the computer, the digital domestic electricity, the communication and so on.
With the development of the microelectronic technique, the scale of the integrated circuits become more and more large, the structure become more and more complex, and the test generation for the integrated circuits is becoming increasingly difficult and time consuming. The traditional test generation algorithms are extremely inefficient for the large-scale circuits. Consequently, new and cost-effective algorithms are imperative research subjects today.
The single stuck-at fault model for combinational circuit is a fault model researched at the earliest internationally, and it is also the one used mostly. Practice shows that the test set for single stuck-at fault can test other kind fault, e.g. multi-fault and bridging fault, if only fault coverage for single stuck-at fault attains above 90%. Because the probability of happening multi-fault for system is big during debug phase and the possibility of happening single fault is bigger during usage phase, the test generation problem for single stuck-at fault is the hot spot of research internationally. On paper, it has solved earlier than 60 times. But theoretical analyze proofs that time complexity for automatic test generation is a NP-completeness problem. As the augment of circuit scale, test generation becomes more and more difficult. Therefore, accelerating test generation and improving its efficiency is noticed all along.
This paper uses the single stuck-at fault model and selects the combinational circuits as research targets. It mainly aims to improve the fault coverage and reduce the test generation time. The main contents are as following:
1. The development and current research status of the test generation is introduced in this paper.
2. The test generation algorithm for non-robust path delay fault in combination- al circuits is studied.
3. Test generation algorithm based on search state dominance for combinational circuits is studied.
4. A test generation algorithm in combinational circuits is studied.
Keywords test generation, stuck-at fault, delay fault
目录
摘 要 I
Abstract III
第1章 绪论 1
1.1 测试生成算法的相关概念 2
1.1.1 测试生成的基本概念 .2
1.1.2 故障模型及模型化故障 3
1.2 测试生成算法概述 6
1.2.1 测试生成算法的研究现状 6
1.2.2 测试生成的发展趋势 8
1.3 课题的背景及研究内容 9
1.3.1 课题的背景 9
1.3.2 课题的主要研究内容 10
第2章 基于时滞故障的组合电路测试生成算法 11
2.1 时滞故障测试的基本知识 11
2.1.1 时滞故障模型 11
2.1.2 时滞测试的硬件模型 12
2.1.3 鲁棒性测试与非鲁棒性测试 13
2.2 基于固定型故障测试生成的时滞故障测试生成 14
2.2.1 基本知识 15
2.2.2 算法描述 17
2.2.3 实验结果 19
2.3本章小结 19
第3章 基于状态控制的组合电路测试生成算法 20
3.1 ..
