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毕业设计:基于cpld的频率测量计,共40页,字数总计:16553毕业设计:基于cpld的频率测量计摘要本文提出了一种基于cpld的数字频率计的设计方法。复杂可编程逻辑器件(cpld)具有集成度高、运算速度快、开发周期短等特点,它的出现,改变了数字电路的设计方法,增强了设计的灵活性。该设计电路简洁,软件潜力得到充分挖掘,低频段测量精度高,有效防止了干扰的...
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共40页,字数总计:16553
毕业设计:基于CPLD的频率测量计
摘 要
本文提出了一种基于CPLD的数字频率计的设计方法。复杂可编程逻辑器件(CPLD)具有集成度高、运算速度快、开发周期短等特点,它的出现,改变了数字电路的设计方法,增强了设计的灵活性。该设计电路简洁,软件潜力得到充分挖掘,低频段测量精度高,有效防止了干扰的侵入。从实验结果上看,采用CPLD设计的电子电路,可以弥补传统硬件电子电路设计中的不足。该频率计利用等精度的设计方法,克服了基于传统测频原理的频率计的测量精度随被测信号频率的下降而降低的缺点。等精度的测量方法不但具有较高的测量精度,而且在整个频率区域保持恒定的测试精度。该频率计利用CPLD来实现频率、周期、脉宽的测量计,完成整个测量电路的测试控制、数据处理和显示输出。并详细论述了硬件电路的组成和软件控制流程。其中硬件电路包括键控制模块、显示模块、输入信号整形模块以及CPLD主控模块。CPLD采用VHDL语言编写,根据控制信号不同进行计数,并且输出计数值到其接口中。本系统测量对象为方波、三角波、正弦波等等,测量范围为1Hz-1MHz输入信号经过放大整形后接入CPLD电路。
关键词:数字频率计;CPLD;等精度
Abstract
This paper produces a CPLD-based digital frequency meter’s design method. complex programmable logic device (CPLD) has the of characteristics of highly integrated, high computing speed, shorter development cycle and so on, the appearance of it changes the methods of digital circuit design, and enhances design flexibility. this paper produces a CPLD-based digital frequency meter’s design method. This design’s circuit is simple, software’s potential is fully tapped and low-frequency measurements have high accuracy, effectively preventing the intrusion of the interference. The experimental results from the point of view, the use of CPLD design of electronic circuits can make up for the traditional hardware designing electronic. Circuit’s deficiencies. The use of such precision frequency meter design ways to overcome the traditional frequency measurement based on the principle of the measurement precision frequency meter with a decline in the measured signal frequency decreases the shortcomings. And other precision measurement method not only has high accuracy, but in the entire frequency region to maintain a constant precision. The frequency meter using CPLD to implement the frequency, period, pulse width and duty cycle measurement count.CPLD is written in VHDL language and counts according to different control signals translate from MCU part, finally, CPLD part will output the count result to the MCU part. The measured objects of the system are square wave, tri-angel wave, sine wave, etc., input signal is shaped after amplifying measurement ranges from 1Hz to 1MHz.
Keywords: Equal Precision; Frequency Meter; CPLD
目 录
1 绪 论 1
1.1 本设计的目的和意义 1
1.2 频率测量计国内外现状及发展趋势 2
1.3 本设计要求 3
1.4 系统设计指标 3
2 方案论证 4
2.1频率计结构框图 4
2.2测量方法论证 4
2.3 显示部分的方案提出及比较 6
2.4 键盘部分的方案提出及比较 7
2.5 控制核心的方案提出及比较 8
3 硬件电路设计 12
3.1 频率计的系统级总体结构框图 12
3.2 CPLD的芯片选择 14
3.3 测量电路的设计 17
3.3.1 频率的测量 18
3.3.2 脉冲宽度的测量 19
3.4 键盘部分的设计 20
3.5 显示部分的设计 20
3.6 电源部分的设计 23
4 软件电路的设计 24
4.1 主程序流程图 24
4.2 VHDL程序设计 26
5 结论 29
致 谢 30
参考文献 31
毕业设计:基于CPLD的频率测量计
摘 要
本文提出了一种基于CPLD的数字频率计的设计方法。复杂可编程逻辑器件(CPLD)具有集成度高、运算速度快、开发周期短等特点,它的出现,改变了数字电路的设计方法,增强了设计的灵活性。该设计电路简洁,软件潜力得到充分挖掘,低频段测量精度高,有效防止了干扰的侵入。从实验结果上看,采用CPLD设计的电子电路,可以弥补传统硬件电子电路设计中的不足。该频率计利用等精度的设计方法,克服了基于传统测频原理的频率计的测量精度随被测信号频率的下降而降低的缺点。等精度的测量方法不但具有较高的测量精度,而且在整个频率区域保持恒定的测试精度。该频率计利用CPLD来实现频率、周期、脉宽的测量计,完成整个测量电路的测试控制、数据处理和显示输出。并详细论述了硬件电路的组成和软件控制流程。其中硬件电路包括键控制模块、显示模块、输入信号整形模块以及CPLD主控模块。CPLD采用VHDL语言编写,根据控制信号不同进行计数,并且输出计数值到其接口中。本系统测量对象为方波、三角波、正弦波等等,测量范围为1Hz-1MHz输入信号经过放大整形后接入CPLD电路。
关键词:数字频率计;CPLD;等精度
Abstract
This paper produces a CPLD-based digital frequency meter’s design method. complex programmable logic device (CPLD) has the of characteristics of highly integrated, high computing speed, shorter development cycle and so on, the appearance of it changes the methods of digital circuit design, and enhances design flexibility. this paper produces a CPLD-based digital frequency meter’s design method. This design’s circuit is simple, software’s potential is fully tapped and low-frequency measurements have high accuracy, effectively preventing the intrusion of the interference. The experimental results from the point of view, the use of CPLD design of electronic circuits can make up for the traditional hardware designing electronic. Circuit’s deficiencies. The use of such precision frequency meter design ways to overcome the traditional frequency measurement based on the principle of the measurement precision frequency meter with a decline in the measured signal frequency decreases the shortcomings. And other precision measurement method not only has high accuracy, but in the entire frequency region to maintain a constant precision. The frequency meter using CPLD to implement the frequency, period, pulse width and duty cycle measurement count.CPLD is written in VHDL language and counts according to different control signals translate from MCU part, finally, CPLD part will output the count result to the MCU part. The measured objects of the system are square wave, tri-angel wave, sine wave, etc., input signal is shaped after amplifying measurement ranges from 1Hz to 1MHz.
Keywords: Equal Precision; Frequency Meter; CPLD
目 录
1 绪 论 1
1.1 本设计的目的和意义 1
1.2 频率测量计国内外现状及发展趋势 2
1.3 本设计要求 3
1.4 系统设计指标 3
2 方案论证 4
2.1频率计结构框图 4
2.2测量方法论证 4
2.3 显示部分的方案提出及比较 6
2.4 键盘部分的方案提出及比较 7
2.5 控制核心的方案提出及比较 8
3 硬件电路设计 12
3.1 频率计的系统级总体结构框图 12
3.2 CPLD的芯片选择 14
3.3 测量电路的设计 17
3.3.1 频率的测量 18
3.3.2 脉冲宽度的测量 19
3.4 键盘部分的设计 20
3.5 显示部分的设计 20
3.6 电源部分的设计 23
4 软件电路的设计 24
4.1 主程序流程图 24
4.2 VHDL程序设计 26
5 结论 29
致 谢 30
参考文献 31