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关于fpga的毕设论文英文翻译文献(外文原文+中文翻译),[1] using fpga technology towards the design of an adaptive fault tolerant frameworkerdogan, sevki (university of hawaii); gersting, judith l.; shaneyfelt, ted;...
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[1] Using FPGA technology towards the design of an adaptive fault tolerant framework
Erdogan, Sevki (University of Hawaii); Gersting, Judith L.; Shaneyfelt, Ted; Duke, Eugene L. Source: Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, v 4, IEEE Systems, Man and Cybernetics Society, Proceedings - 2005 International Conference on Systems, Man and Cybernetics, 2005, p 3823-3827
ISSN: 1062-922X CODEN: PICYE3
Conference: IEEE Systems, Man and Cybernetics Society, Proceedings - 2005 International Conference on Systems, Man and Cybernetics, Oct 10-12 2005, Waikoloa, HI, United States Sponsor: IEEE Systems, Man and Cybernetics Society
Publisher: Institute of Electrical and Electronics Engineers Inc.
Abstract: In this paper we propose architecture for a Reconfigurable, Adaptive, Fault-Tolerant (RAFT) framework for application in real time systems with require multiple levels of redundancy and protection. Typical application environments include distributed processing, fault-tolerant computation, and mission and safety-critical systems. The framework uses Field Programmable Gate Array (FPGA) technologies with on the fly partial programmability achieving reconfiguration of a system component when the existing components fail or to provide extra reliability as required in the specification. The framework proposes the use an array of FPGA devices to implement a system that, after detecting an error caused by a fault, can adaptively reconfigure itself
摘要1:
本文目的是提出构建一个有自适应和容错(筏)性质的框架，它应用在需要多层次的冗余保护的实时系统, 典型应用环境包括分布式处理,容错计算,和任务与安全至关重要的系统. 该框架采用了现场可编程门阵列( FPGA )技术的飞局部可编程功能实现重构系统组件，当现有的组件损坏或未能提供额外可靠性所要求的规格时，可以重构系统. 该框架提出使用一组现场可编程门阵列器件实现一种系统, 这种系统 经过检测一个错误所造成的过失,可通过自适应重构实现容错. 在现场可编程门阵列中,通过定义了一种系统模式,使对系统用户定义不同级别的可靠性选择,提供一个监督层的系统工程师，使其提供越来越广泛地成为一个低成本的开发。
Erdogan, Sevki (University of Hawaii); Gersting, Judith L.; Shaneyfelt, Ted; Duke, Eugene L. Source: Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics, v 4, IEEE Systems, Man and Cybernetics Society, Proceedings - 2005 International Conference on Systems, Man and Cybernetics, 2005, p 3823-3827
ISSN: 1062-922X CODEN: PICYE3
Conference: IEEE Systems, Man and Cybernetics Society, Proceedings - 2005 International Conference on Systems, Man and Cybernetics, Oct 10-12 2005, Waikoloa, HI, United States Sponsor: IEEE Systems, Man and Cybernetics Society
Publisher: Institute of Electrical and Electronics Engineers Inc.
Abstract: In this paper we propose architecture for a Reconfigurable, Adaptive, Fault-Tolerant (RAFT) framework for application in real time systems with require multiple levels of redundancy and protection. Typical application environments include distributed processing, fault-tolerant computation, and mission and safety-critical systems. The framework uses Field Programmable Gate Array (FPGA) technologies with on the fly partial programmability achieving reconfiguration of a system component when the existing components fail or to provide extra reliability as required in the specification. The framework proposes the use an array of FPGA devices to implement a system that, after detecting an error caused by a fault, can adaptively reconfigure itself
摘要1:
本文目的是提出构建一个有自适应和容错(筏)性质的框架，它应用在需要多层次的冗余保护的实时系统, 典型应用环境包括分布式处理,容错计算,和任务与安全至关重要的系统. 该框架采用了现场可编程门阵列( FPGA )技术的飞局部可编程功能实现重构系统组件，当现有的组件损坏或未能提供额外可靠性所要求的规格时，可以重构系统. 该框架提出使用一组现场可编程门阵列器件实现一种系统, 这种系统 经过检测一个错误所造成的过失,可通过自适应重构实现容错. 在现场可编程门阵列中,通过定义了一种系统模式,使对系统用户定义不同级别的可靠性选择,提供一个监督层的系统工程师，使其提供越来越广泛地成为一个低成本的开发。
