简易逻辑分析仪的设计.doc
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简易逻辑分析仪的设计,全文27页约5300字论述翔实目录一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3二、英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4三、 概 述 - - - - - -...
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此文档由会员 花季永驻 发布
简易逻辑分析仪的设计
全文27页 约5300字 论述翔实
目录
一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3
二、 英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4
三、 概 述 - - - - - - - - - - - - - - - - - - - - - - - - 6
四、 总体方案设计 - - - - - - - - - - - - - - - - - - - - - - - 6
4.1、 方案比较与选择- - - - - - - - - - - - - - - - - - - - - -6
4.2、 统设计方案 - - - - - - - - - - - - - - - - - - - - - - - -7
五、 电路分析与设计- - - - - - - - - - - - - - - - - - - - - - -8
5.1 信号发生器- - - - - - - - - - - - - - - - - - - - - - - - -8
5.2 输入电路- - - - - - - - - - - - - - - - - - - - - - - - - 10
5.3 采集与存储电路-- - - - - - - - - - - - - - - - - - - - - 11
5.4 显示控制电路- - - - - - - - - - - - - - - - - - - - - - - 11
5.5 利用示波器显示：- - - - - - - - - - - - - - - - - - - - - -13
5.6 电源 - - - - - - - - - - - - - - - - - - - - - - - - - 15
六、 软件设计- - - - - - - - - - - -- - - - - - - - - - - - -17
七、 系统测试分析 - - - - - - - - - - - - - - - - - - - - - - -19
八、 结论- - - - - - - - - - - - - - - - - - - - - - - - - -22
九、 结束语 - - - - - - - - - - - - - - - - - - - - - - - - -23
十、 参考文献- - - - - - - - - - - - - - - - - - - - - - - - -24
十一、 致谢 - - - - - - - - - - - - - - - - - - - - - - - - - - 25
摘 要
逻辑分析仪是一种新型的数字测试仪器。它应用于微机等数字系统的软件、硬件调试，故障检查，性能分析等过程中。它可以监测硬件电路工作时的逻辑电平，并加以存储，用图形的方式直观地表达出来，便于用户检测，分析电路设计中的错误。在数字电路调试中，往往要测试多路信号波形，分析其逻辑关系。普通示波器最多只能测试两路信号波形，而逻辑分析仪价格较高，我们设计的简易逻辑分析仪造价低、性能高，具有一定的推广价值。
本系统采用单片机和CPLD结合的方式。用CPLD制作信号发生和采集装置，产生8路信号及数据采集。信号发生器的序列时钟频率可高于100HZ 。系统触发方式具有单级触发字和三级逻辑状态分析触发功能。其中触发字可以通过键盘任意设定，触发位置可调。
此逻辑分析仪能够在示波器上清晰稳定地显示所采集到的8路信号波形和时间标志线，并显示触发点的位置。单片机输出可在上位机上显示，能同时看到八路信号的波形和同一时刻不同信号的逻辑状态。系统利用单片机来完成人机界面控制，信号触发、分析、处理与变换。 8位输入电路的输入阻抗大于50kΩ,门限电压16级
可调。每通道的存储深度可达到32bit。单片机与CPLD的结合简化了外围硬件电路的设计，增加了系统的稳定性和可靠性。
关键字：单片机,CPLD,逻辑分析仪,示波器,信号发生器
ABSTRACT
Logic analyzer is a new-style digital testing instrument. It be used in the test of software and hardware of digital system, such as micro-computer,, fault-checked ,analysing-performance. It can surrey the voltage logic when system in full power. The instrument can save the result and describe it in figure for surveying and analyzing the error in circuit design. It need test multi-channel signal to analyse its logic relation in digital circuit testing .It only can test two signal for common oscillograph..Logic analyzer is expensive. Simple logic analyzer have low cost and high performance .It is worthy of using widely .
This system combines 89C51 and CPLD generating eight-channel signal and gathering data. The frequency of signal trigger’s clock is more than 100MHZ. The system trigger method has two ways one is single level trigger word the another is tri-level trigger function of logic analysis. Further more the trigger word can be modified through the keyboard. The trigger position can be changed freely.
This Logic analyzer output that is 8-channel signal wave gathered from outside and the time flag can be display on the oscillograph screen steadily. The oscillograph show the position of trigger point. The 89C51 communicates with PC to show it’s output. Users can observe eight channels signal wave and the signal states of different logic at the same time. The system accomplishs the interface of control between user and 89C51,signal touching off, analysis, disposing, and transform. The impedance of eight-channel signal input circuit is more than 50kΩ. The alterable voltage boundary is divided into16levels. The storage’s deep is up to 32bit. This combination of 89C51 and CPLD predigests the design of periphery instruments. This improvement let system became more stable and reliable.
Key words: micro-computer, CPLD, Logic analyzer,
oscillograph, signal generator.
部分参考文献
《单片机应用选编》
北京航空航天大学出版社
《新编电子电路大全》
中国计量出版社
《集成电路500例》
人民邮电出版社
全文27页 约5300字 论述翔实
目录
一、 中文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -3
二、 英文摘要 - - - - - - - - - - - - - - - - - - - - - - - - -4
三、 概 述 - - - - - - - - - - - - - - - - - - - - - - - - 6
四、 总体方案设计 - - - - - - - - - - - - - - - - - - - - - - - 6
4.1、 方案比较与选择- - - - - - - - - - - - - - - - - - - - - -6
4.2、 统设计方案 - - - - - - - - - - - - - - - - - - - - - - - -7
五、 电路分析与设计- - - - - - - - - - - - - - - - - - - - - - -8
5.1 信号发生器- - - - - - - - - - - - - - - - - - - - - - - - -8
5.2 输入电路- - - - - - - - - - - - - - - - - - - - - - - - - 10
5.3 采集与存储电路-- - - - - - - - - - - - - - - - - - - - - 11
5.4 显示控制电路- - - - - - - - - - - - - - - - - - - - - - - 11
5.5 利用示波器显示：- - - - - - - - - - - - - - - - - - - - - -13
5.6 电源 - - - - - - - - - - - - - - - - - - - - - - - - - 15
六、 软件设计- - - - - - - - - - - -- - - - - - - - - - - - -17
七、 系统测试分析 - - - - - - - - - - - - - - - - - - - - - - -19
八、 结论- - - - - - - - - - - - - - - - - - - - - - - - - -22
九、 结束语 - - - - - - - - - - - - - - - - - - - - - - - - -23
十、 参考文献- - - - - - - - - - - - - - - - - - - - - - - - -24
十一、 致谢 - - - - - - - - - - - - - - - - - - - - - - - - - - 25
摘 要
逻辑分析仪是一种新型的数字测试仪器。它应用于微机等数字系统的软件、硬件调试，故障检查，性能分析等过程中。它可以监测硬件电路工作时的逻辑电平，并加以存储，用图形的方式直观地表达出来，便于用户检测，分析电路设计中的错误。在数字电路调试中，往往要测试多路信号波形，分析其逻辑关系。普通示波器最多只能测试两路信号波形，而逻辑分析仪价格较高，我们设计的简易逻辑分析仪造价低、性能高，具有一定的推广价值。
本系统采用单片机和CPLD结合的方式。用CPLD制作信号发生和采集装置，产生8路信号及数据采集。信号发生器的序列时钟频率可高于100HZ 。系统触发方式具有单级触发字和三级逻辑状态分析触发功能。其中触发字可以通过键盘任意设定，触发位置可调。
此逻辑分析仪能够在示波器上清晰稳定地显示所采集到的8路信号波形和时间标志线，并显示触发点的位置。单片机输出可在上位机上显示，能同时看到八路信号的波形和同一时刻不同信号的逻辑状态。系统利用单片机来完成人机界面控制，信号触发、分析、处理与变换。 8位输入电路的输入阻抗大于50kΩ,门限电压16级
可调。每通道的存储深度可达到32bit。单片机与CPLD的结合简化了外围硬件电路的设计，增加了系统的稳定性和可靠性。
关键字：单片机,CPLD,逻辑分析仪,示波器,信号发生器
ABSTRACT
Logic analyzer is a new-style digital testing instrument. It be used in the test of software and hardware of digital system, such as micro-computer,, fault-checked ,analysing-performance. It can surrey the voltage logic when system in full power. The instrument can save the result and describe it in figure for surveying and analyzing the error in circuit design. It need test multi-channel signal to analyse its logic relation in digital circuit testing .It only can test two signal for common oscillograph..Logic analyzer is expensive. Simple logic analyzer have low cost and high performance .It is worthy of using widely .
This system combines 89C51 and CPLD generating eight-channel signal and gathering data. The frequency of signal trigger’s clock is more than 100MHZ. The system trigger method has two ways one is single level trigger word the another is tri-level trigger function of logic analysis. Further more the trigger word can be modified through the keyboard. The trigger position can be changed freely.
This Logic analyzer output that is 8-channel signal wave gathered from outside and the time flag can be display on the oscillograph screen steadily. The oscillograph show the position of trigger point. The 89C51 communicates with PC to show it’s output. Users can observe eight channels signal wave and the signal states of different logic at the same time. The system accomplishs the interface of control between user and 89C51,signal touching off, analysis, disposing, and transform. The impedance of eight-channel signal input circuit is more than 50kΩ. The alterable voltage boundary is divided into16levels. The storage’s deep is up to 32bit. This combination of 89C51 and CPLD predigests the design of periphery instruments. This improvement let system became more stable and reliable.
Key words: micro-computer, CPLD, Logic analyzer,
oscillograph, signal generator.
部分参考文献
《单片机应用选编》
北京航空航天大学出版社
《新编电子电路大全》
中国计量出版社
《集成电路500例》
人民邮电出版社
